This invention relates to integrated circuit devices such as field-programmable gate arrays (“FPGAs”), and more particularly to circuitry on FPGAs that can be used to transmit and/or receive data signals in multiple channels.
An integrated circuit such as an FPGA may be provided with multiple channels of circuitry for transmitting and/or receiving data. These channels may be grouped into several groups of channels. Each group may receive a reference clock signal. For greater flexibility of use of the circuitry, it may be desirable to be able to use the reference clock signal received by any of the groups in that group and/or in any others of the groups. Any such distribution or sharing of clock signals among the groups is preferably done as efficiently as possible. This is aided by performing the clock signal distribution—including any necessary buffering of the signals—within the circuitry of the groups. It is also desirable for the circuitry of all of the groups to be the same or substantially the same, e.g., because this facilitates design and verification of the circuitry.
Similar considerations may apply to other signals that may need to be communicated to the groups. Examples of such other signals are calibration control signals, which may be used for such purposes as controlling the effective values of circuit elements that provide terminations of data signal connections to circuitry external to the integrated circuit device.
Improved clock and other signal distribution circuitry that will help satisfy criteria such as those identified above is needed.